The present invention generally relates to the field of semiconductors, and more particularly relates to a method of fabricating metallization structures, BEOL metallization layers, and the like, on semiconductor substrates.
Semiconductor wafers, chips, devices, and the like, whether including analog or digital electronic circuits, typically rely on at least one metallization layer disposed on a semiconductor substrate to provide electronic interconnections between circuits on the semiconductor substrate or layer. Some circuit designs use a plurality of metallization layers stacked on top of one another. A metallization layer may also be referred to as a back-end-of-line (BEOL) metallization layer which could be disposed on a semiconductor material stack. Semiconductor contacts in a top layer in the semiconductor material stack are electrically connected to metal contacts and metal interconnects in a metallization layer disposed on the semiconductor material stack.
As chip designs continue to miniaturize on-chip electronic device dimensions to increase feature density, such chip designs attempt to locate electronic devices, and accordingly device features, closer and closer to each other on a semiconductor chip. As device features are located closer to each other, the respective metal interconnection wires are smaller widths and separated from each other by smaller pitch values and tighter pitch tolerances (pitch variability), to meet chip design requirements. As pitch values between adjacent features become much smaller with tighter pitch tolerances, conventional metal interconnection wires and contacts experience fabrication processing problems to meet the smaller metal interconnection wire widths, smaller metal contacts, and tighter pitch requirements. These fabrication processing problems can be magnified when a semiconductor stack design electrically interconnects metal contacts in a metallization layer with semiconductor contacts in a semiconductor layer. Scaling circuit designs to smaller physical layouts is getting more difficult because of the conflict between design requirements and layout restrictions at the contact and local interconnected level. These types of limitations of metal interconnection wire and electrical contact design, at continuously smaller scale circuit designs, have created a challenge for circuit designers and for semiconductor fabrication process designers to continue to meet further miniaturization goals. In order to resolve such difficulties and limitations, new semiconductor fabrication process elements and semiconductor structures will be required.